The present invention relates to the fabrication of a bipolar transistor in LSI or VLSI technology featuring shallow junctions for high switching speed and capable of a high packing density.
There has been a great demand for a bipolar transistor capable of a high packing density and high speed switching formed in a VLSI process. One suggested process for achieving these goals is known as a polysilicon self-aligned or PSA. The PSA process, however, incorporates complex etching steps and a double polysilicon sequence which makes the overall flow difficult to manufacture and the obtainable yields low. Another method of obtaining high speed circuits is through sidewall base contact structures. Again complexity of processing, as well as a large number of photolithography levels make the latter structures difficult to manufacture. Other methods utilize a basic bipolar transistor profile with additions such as trench isolation rather than oxide isolation. Such devices have not been able to achieve maximum speed, however.
Accordingly, it is an object of the present invention to provide a bipolar transistor cell formed in a VLSI process which has improved switching speed and is capable of a high packing density.